Cognichip wants AI to design the chips that power AI, and just raised $60M to try

Cognichip has raised a $60 million round to build AI tools for semiconductor design, with Seligman Ventures leading and Lip-Bu Tan joining the board. That brings the startup to $93 million raised since its 2024 launch.

The pitch is straightforward: build a domain-specific AI model that helps hardware teams write RTL, tune constraints, guide floorplanning, and shave time off the long, expensive path from spec to tapeout.

The target is real enough. AI companies talk about model scale and giant clusters, but somebody still has to design the chips, package them, verify them, and get them through signoff without spending years and burning through tens of millions of dollars.

That’s where Cognichip wants to be.

Why people care

Chip design has had a tooling problem for years. The workflows are mature, but they’re also brittle, expensive, and packed with specialized knowledge. A modern AI accelerator can take three to five years to get from architecture to production. At advanced nodes, mask costs alone can top $50 million. Nvidia’s Blackwell-class parts push past 100 billion transistors. Small choices pile up fast.

So the timing makes sense. AI demand already pushed the industry harder toward custom silicon. Using AI to cut manual work in the design flow is an obvious next bet.

Cognichip CEO Faraj Aalaei is making that case aggressively. The company says its system can cut development cost by more than 75% and shorten schedules by more than half. Those are huge claims, and right now they look far ahead of the evidence. Cognichip hasn’t shown a full production chip designed end to end with its system, and it hasn’t named customers. It says it has worked with design teams since September 2025.

For now, this is a bet on direction, not proof.

What the product likely looks like

Cognichip says its software is built around a model trained on semiconductor design artifacts and workflows, not a general-purpose LLM pointed at hardware. That matters.

Generic coding models can spit out plausible-looking SystemVerilog. Plausible is dangerous in hardware. A bad suggestion can clear syntax, survive a basic simulation, and still turn into a timing failure, a verification hole, or a silicon bug.

A chip design copilot has to do at least four things well.

Work with front-end design data

That means turning specs into RTL, interfaces, and assertions in SystemVerilog or VHDL, while following the team’s own rules. Naming conventions, reset strategy, clock-domain assumptions, bus protocols, all of it matters. A decent model should pull from prior internal designs and follow those patterns instead of inventing new ones every time.

Help with verification

This is where a lot of AI demos fall apart. Generating the module is the easy part. You still need UVM scaffolding, SVA properties, constrained-random coverage, and some way to spot the corner cases the model missed. If the tool can read logs, summarize waveform failures, and suggest directed tests, that’s useful.

Steer implementation

Physical design is full of ugly optimization loops. Constraints in SDC, floorplan choices, congestion, buffering, routing, power intent in UPF, timing closure across corners. Existing EDA vendors already use machine learning and reinforcement learning here. Synopsys DSO.ai and Cadence Cerebrus are the obvious benchmarks. Cognichip is trying to connect those back-end decisions with front-end generation.

Learn from actual tool outputs

This is the part that matters most. Generating HDL text isn’t the hard part. The hard part is whether the system can make a proposal, run it through synthesis or signoff flows, score the result, and improve the next pass. Without that loop, it’s autocomplete dropped into one of the hardest engineering domains around.

The hard part is also the moat

Semiconductor data doesn’t look anything like public web code. The valuable material is locked behind NDAs, buried in internal repos, or tied up in foundry agreements. There is no GitHub-scale corpus of production RTL, SDC, LEF/DEF, signoff reports, and bug histories sitting there for the taking.

Cognichip says it’s dealing with that in three ways:

• synthetic datasets
• licensed partner data
• secure fine-tuning on proprietary customer inputs

That’s plausible. It also comes with limits.

Synthetic corpora can teach structure. You can vary pipeline depth, protocol timing, bus width, cache parameters, and so on. That helps with grammar and common design patterns. It doesn’t teach the strange failure modes that show up in real SoCs after months of verification work.

Licensed partner data is better, assuming there’s enough of it and enough variation in it. Quality matters more than raw volume here. A thousand weak examples won’t beat a smaller set of real designs tied to implementation and bug outcomes.

Secure fine-tuning is mandatory. No serious hardware team is going to pour proprietary IP into a shared cloud model and shrug. If Cognichip wants enterprise adoption, it needs on-prem or isolated VPC deployments, strong audit logging, and clear answers on data retention. Confidential compute support like AMD SEV-SNP or Intel TDX helps, but most buyers will still ask the blunt question first: where does our IP live?

Up against Synopsys and Cadence

Cognichip is not entering an open field. Synopsys and Cadence already own the workflow. They already ship ML-assisted tooling for PPA optimization and search. They already sit in the signoff path, where trust matters most.

That gives them two big advantages:

1. They have the integrations.
2. They have the customer data gravity.

A startup can still build a better model. It can move faster on workflow design and target the messy handoff points the big EDA suites never cleaned up. But to matter, it still has to fit into Innovus, ICC2, verification stacks, foundry decks, and the rest of the production environment engineers already use.

“EDA copilot” is probably the right framing. Full autonomy is a weak near-term pitch for chip design. Assistive tooling is much easier to believe. Engineers will use a system that drafts RTL, proposes assertions, suggests placement changes, or triages regressions, as long as the outputs are inspectable and the claims hold up in the normal flow.

Nobody sane is giving tapeout authority to a chatbot.

What senior engineers should watch

If you run hardware, infrastructure, or platform teams, the useful question is narrow: where can a model cut expensive human iteration without adding risk you can’t tolerate?

A few areas stand out:

• Reusable block generation: interconnects, DMA engines, bridges, wrappers, register blocks
• Verification grunt work: testbench scaffolding, assertion drafts, failure clustering, coverage gap suggestions
• Constraint tuning: proposing SDC updates or placement adjustments based on prior runs
• Design reuse mining: finding similar internal blocks and adapting them faster than a human grep session

The more structured design history your team already has, the better these systems should work. That may be the bigger strategic point. The best input for this kind of tooling probably won’t be internet-scale data. It’ll be your own past projects, regressions, timing reports, and signoff outcomes, cleaned up and versioned.

Teams that treat design artifacts as training and retrieval infrastructure will have an edge. Teams with messy repos and tribal knowledge won’t.

Big claims, thin proof

Cognichip says it can cut cost by 75% and timelines by half. Maybe on narrow slices of the flow. Maybe on smaller or mid-complexity blocks. Maybe for teams buried in repetitive work.

Across full-chip programs, those numbers sound early.

Chip design schedules don’t come from one slow step. They come from chains of dependencies, validation loops, and physical constraints that punish bad assumptions. A model can speed up drafting and exploration. That matters. It does not remove the need for verification closure, signoff confidence, or somebody taking responsibility when a bug ships in silicon.

Hardware teams are conservative for good reasons. Software bugs are patchable. Tapeout mistakes are expensive souvenirs.

Still, the category is real. AI-assisted EDA is past the toy-demo stage. The incumbents already showed that ML can improve optimization loops. The next fight is whether a startup can combine language models, graph models, and tool orchestration into something engineers will trust in daily work.

That’s much harder than generating SystemVerilog from a prompt. It’s also the only version that matters.

If Cognichip can show real customer wins on production flows, with measurable gains in iteration time and solid answers on IP security, people will take it seriously fast. Until then, the funding is a vote on the problem, not the solution.